TSMC claims that its SoIC-X interconnection has very low impedance, which means that COUPE is very efficient in terms of power usage. The development trajectory of COUPE has three major phases.

TSMC's new 2nm Kaohsiung fab is reportedly 6 months ahead of schedule, TSMC hosts equipment move-in ceremony to clients, ...

TSMC is strategically developing a dedicated supply chain cluster on 30 hectares (300,000 square meters) of land in Southern ...

TSMC says the initial version of System-on-Wafer ... design and putting its system-on-integrated chips (SoIC) on top of it, allowing it to stack logic and memory directly on top of a wafer-sized ...

The fab is prepared for mass production of TSMC-SoIC™ (System on Integrated Chips) process technology. Advanced Backend Fab 6 enables TSMC to flexibly allocate capacity for TSMC 3DFabric™ advanced ...

Apple is reportedly one of TSMC's first clients of its new 2nm process node, making its A19 Pro chip for the iPhone 17, and its new M5 chip with SoIC advanced packaging (SoIC = Small Outline ...

3D Chip Stacking – TSMC announced SoIC-P, microbump versions of its System on Integrated Chips (SoIC) solutions providing a cost-effective way for 3D chip stacking. SoIC-P complements TSMC’s existing ...

and Small Outline Integrated Circuits (SOIC) which provide it an additional competitive advantage. These technologies enhance the performance and efficiency of AI chips, giving TSMC a critical ...

TSMC (TSM) suspended shipments to China-based chip designer Sophgo after a chip it made was found on a Huawei AI processor, Reuters’ Karen Freifeld and Fanny Potkin report, citing two people ...